AMD Leaps Ahead with Zen Architecture Powered EYPC Processors for the Cloud

AMD CVP Robert Hormuth was on hand at Cloud Field Day to share his views on cloud native computing and how his architect team at AMD has tackled EPYC processor development to deliver the right performance for cloud native environments. Why would architecture changes matter for an operational computing model? Robert laid out his case by discussing the differences between traditional monolithic computing to virtual/Iaas, Containerized/Caas, and Functionize/FaaS workload management. Each of these stack changes drove underlying changes to the processor architecture. The virtualization era drove higher memory capacity, a move to multicore architectures and some intra VM data locality. In moving to containers, we say higher core counts and increased memory BW, a great reduction in data locality, and more stress on IO performance. Finally, functions have called for maximization of core count and a state of short-lived workload existence.

What has AMD done to address this? First, AMD placed priority on innovating for the future of cloud native workloads over porting the past. With this comes a shift from VMs sharing core hypervisor services across all platform services to the concept of Dom0, a thinner hypervisor interacting with Dom0 services running in a single VM and run on a DPU or smartNIC. The AMD DPU, called Pensando, is integrating high speed packet processing, CPU slow path processing and backside IO to flash, NVMe, Drives, DRAM etc. This buys you more tenant instances, increased enabled applications in the cloud for determinism and performance, consistent management across environments, centralization of security and abstraction of HW+SW services to any host CPU and bare metal OS.

This also comes with a focus on chiplet architectures and acceleration of innovation past Moore’s Law. AMD’s chiplet design enables product innovation mixing and matching cores and architectural features based on different workload requirements as represented by 4 different EPYC product lines under the 4th generation of processor. These chiplets also lower cost of design with incredible flexibility compared to monolithic design. Chiplets with 2.5D and 3D stacking also increase silicon real estate delivering higher silicon area on package and ultimately more cores per CPU and memory to the customer.

So what about CPU acceleration? AMD strongly believes that tenants will want to utilize off the shelf code that have not been optimized for workload acceleration, and that operators benefit not from offering tenants workload acceleration but accelerating core functions through the DPUs and providing high performance standard cores for tenant workloads. This is an interesting view given AMD’s primary competitor has loaded their CPU with 14 workload accelerators.

The TechArena’s take is that both companies are right. Some savvy enterprises will optimize their code to take advantage of workload acceleration, and some of them will run these strategic apps in the cloud. The majority of enterprises do indeed want to run off the shelf code, and AMD’s bet on simplified high-performance cores will pay off over alternatives. Cloud operators likely will continue offering a choice in infrastructure instances to address both customer markets. AMD Bergamo offers 128 core scaling that puts it in the lead for pure performance, and because of this cloud native workloads especially in containerized or functionized environments are ideally suited for these platforms.